University of Bristol

Jose Nunez-Yanez

Hello,

My name is Jose Nunez-Yanez and I am a senior lecturer in the department of Electronic Engineering working in the Microelecronics and Signal Processing group. My research interests include reconfigurable computing, data compression, on-chip communications and processor architecture with a strong focus on energy efficiency.

Research projects in the group involving hardware address the areas of partial dynamic reconfiguration, power management, application specific instruction set processors, stochastic networks on chip and architectures for lossless data compression and video processing. Recent work in the area of video involves video super–resolution and video fusion, for example. Most of our work is based on FPGAs mainly from Xilinx and Altera.  Lately we have been very interested in new high-level programming models from Altera with OpenCL and the Xilinx Vivado HLS tools. OpenCL is fascinating thanks to how easy is to move algorithms among CPU, GPU and FPGA targets. Would it make sense to embed all these computing resources in a single heterogenous chip and shared memory with uniform access ? GPUs are particular strong dealing with kernels with uniform parallelism involving floating point operations but how about other kernels that are more serial or include thread divergence. Can FPGAs do a good job here ?  Interesting questions so contact me if you would like to collaborate to find answers. 


 

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